| Date | Topic | Reading | Handouts | Assignments |
|---|---|---|---|---|
| Aug 26 | Welcome Course Policies Intro to Digital | Chp 1 PPT | ||
| Aug 28 | No Class (Instructor Out) | |||
| Sep 2 | Basic Gates (and, or, not) Intro to Binary Lab Discussion | Chp 3 PPT Simulations | Lab 1 - Basic Logic Gates. Make sure you demo each circuit to the instructor for sign off. Due end of lab. Corrected Link to "The Pull-up Resistor" is https://archive.seattlerobotics.org/encoder/199703/basics.html | |
| Sep 4 | Basic Gates (cont) Number Systems | Number Systems (Bin, Hex, Oct) | Chp 2 PPT | HW #1 - Number Conversions (due Sep 9 at start of class). Submit via same link for instant feedback AND submit hand written work at start of class for credit and only one submission will be accepted for this assignment! |
| Sep 9 | Logic Circuits Combining Gates Deriving Truth Table Deriving Boolean Equation | Typed notes Simulations | HW #2 - Due next class (Sep 11) at start of class (paper copy). Lab #2 - Due end of lab. | |
| Sep 11 | Boolean Algebra | Notes (Prev Year, but same material) Boolean Algebra Rules Sheet | HW #3 Due start of next class (Sep 16). Turn in hand written work. | |
| Sep 16 | Boolean Algebra (Cont) | Notes (Prev Year, but same material) DeMoregan's Theorem Chp 7 (All About Circuits) | HW #4 Due at start of class Sep 23 Lab #3 - Due end of lab. | |
| Sep 18 | TEST #1 All material covered up to the start of boolean algebra (Lecture Sep 11), Lab #1 and Lab #2 (exclude question on boolean algebra minimization) | |||
| Sep 23 | Go over HW #4 SOP and Demorgan Universal Gates | SOP/POS Handout SOP/POS Simulation Universal Gates Universal Gate Simulation Unversal Gates full explanation Example Nand Gate Conversion | HW #5 Due start of next class. Lab #4 - Due in one week. Schematics will be drawn using KiCad. Logic Probe Reading | |
| Sep 25 | Go over HW #5 | HW #6 Due Sep 30 at start of class. | ||
| Sep 30 | Adders, Binary Addition, 2's Comp | 2's Comp | Lecture PPT Lecture Notes | HW #7 Due start of next class. Lab #5 - Due at end of lab. |
| Oct 2 | Complex TTL Devices | Chp 6 | Lecture Notes | |
| Oct 7 | Return Test #1 Answer any questions for Test #2 Discuss Lab #6 | Lab #6 - with a partner, build the Circuit and complete the handout and submit electronically. 7-Seg Datasheet 7447 Datasheet | ||
| Oct 9 | TEST #2 Boolean, Universal Gates. | |||
| Oct 14 | Fall Break | |||