Introduction Computer History
Timeline of Computer History
· History of Intel Processors
· History Lost and Found - Mark I Computer
· History Lost and Found - ENIAC
· History Lost and Found - Transistor
· History Lost and Found - Apple Computer
· The Most Important Invention of the 20th Century: Transistors
|Jan 20||Number System Review
Memory and Bus Architecture
Flip Flops and Latches Review
Digital Buffer and the Tri-State Buffer
Mux / DeMux
Memory (Note: This chapter goes into greater detail than required for this class.)
(including how to access simulations)
|Jan 25||Memory and Bus Architecture (cont)||Lab 1 - Due in one week via online submission.|
When originally posted, step 3 stated "it should read 0xAA. This is incorrect (it should read 0x00). It has since been fixed in the document (Ver 1.05 has been corrected).
|Jan 27||CPU Architecture||Internal Architecture||How A CPU Works|
|Feb 1||CPU Architecture (Cont)|
Come ready to ask questions on the "Scott Processor"
ASM and Hand Compiling
6502 Op Codes
|Lab 2 - due in one week. Full Schematic can be found HERE.|
Rigol Scope configuration file can be downloaded HERE.
(note - this must be placed on a FAT32 formated thumbdrive. If you need one, ask the instructor)
Due to limited arduino shields, those who volunteered to build their own will have priority. Other students will be in a lottery of who gets them first (unless we have volunteers to do lab outside of the scheduled time).
Rigol Scope Documentation
Datasheet 6810 Ram IC
|Feb 3||No Class (due to weather)|
|Feb 8||Hand Compiling ASM to ML|
|Class Notes (CORRECTED 2/15/22)||Lab 3|
HW 1 - Due in one week at start of class.
|Feb 10||_delay_ms() trace|
Chp 7 Sec 2
|Feb 15||I/O Cont|
|Lab 4a - When complete, demo to instructor and submit zip file of the project.|
|Bitwise Operators (Reading)|
Tutorial Point Bitwise Opeators in C
|Feb 22||No class or lab - instructor ill|
|Feb 24||No class or lab - instructor ill|
|Mar 1||Bitwise Operators (cont)||Lab 4b|
|Mar 3||ADC||Lecture Notes|
|Mar 7-11||Spring Break|
|Mar 15||No Class|
Work on Lab 5
|Lab 5 - Lab due in one week. Lab and cabinet will be opened by Matt Hale for lab. 10 Turn Pot's are in the cabinet along with arduino boards. (10 Turn Pots have color coded leads: Red +5, Black Ground, Yellow Output).|
Please start using the _BV() method of bit manipulation we discussed in class vs REG=0x__ or REG=(1<<name) we have previously been using.
|Mar 16||ADC (Cont)|
Image 1 2
More Info 1 2 3
Volatile (in C)
|Chp 10 (especially 10.3)|
Chp 9 (TOF)
|Lab 4c - Add speed control to Lab 4b using ADC/Pot from Lab 5|
|Mar 24||Discuss Lab 6|
|Mar 29||Input Capture||TEST #1 - Due Thurs Apr 7 |
Name: your last name (first letter of last name is caps).
Password: Last 4 digits of U number.
Lab 6 - due start of next week's lab.
|Mar 31||Input Capture (cont)||Lecture Notes|
|Apr 5||Input Capture Lab||Lab #7 - Input Capture using TSL237 Light Sensor.|
|Apr 7||Output Compare||Prof Kohn's Output Compare PPT||Lab #8 - Use Output Compare to play the Jeopardy Theme.|
Use this excel spreadsheet that contains the notes and Frequencies to calculate the number of counts per note.
Here is a FULL SIZE version of the Notes to Freq Table. It is best to print in Landscape Mode.
|Apr 12||Work on Lab 8|
|Apr 14||Discuss Final Project||PWM|
SRF05 Untra_Sonic Ranger
|Apr 19||Work on Final Project|
|Apr 21||Work on Final Project||Test #2 - The test is open notes, open book, open references.|
Suggest printing it out, working the problems then coming back to the page, fill in the answers and submit.
To log in, use your last name (with the first letter of your last name in caps). Use the last 4 digits of your U# as your password.
Test Opens Thu Apr 21 at 9:40am and is due Thu Apr 28 by 11:05am.
|Apr 26||Work on Final Project|
|Apr 28||Study Day||Test #2 Due by |
Final Project due by 5pm.