Flip Flops and Latches
Circuit #1 - SR Flip-Flop (NOR)
SR - Flip Flop (NOR) Truth Table
| Set | Reset | Q | Not Q |
| 0 | 0 | Qlast | Not Qlast |
| 0 | 1 | 0 | 1 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | Illegal |
Circuit #2 - Gated SR Flip-Flop (NOR)
Gated SR - Flip Flop (NOR) Truth Table
| Set | Reset | GATE | Q | Not Q |
| X | X | 0 | Qlast | Not Qlast |
| 0 | 0 | 1 | Qlast | Not Qlast |
| 1 | 0 | 1 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | Illegal |
X - Don't Care
Circuit #3 - SR Flip-Flop (NAND)
SR - Flip Flop (NAND) Truth Table
| NOT Set | NOT Reset | Q | Not Q |
| 1 | 1 | Qlast | Not Qlast |
| 1 | 0 | 0 | 1 |
| 0 | 1 | 1 | 0 |
| 1 | 1 | Illegal |
As with the NOR Flip Flop, A gate can be added to the NAND Flip Flop.
Circuit #4 - D Latch
D Latch
| D | C | Q | Not Q |
| X | 0 | Qlast | Not Qlast |
| 1 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 |
Circuit #5 - Edge Trigger
These circuits allow the latch to be triggered (clocked) on the rising or falling edge of a pulse instead on just the ON GATE used in the previous examples.
These circuits work due to PROPAGATION DELAY. Propagation delay is the TIME it takes for a change in the input to be seen on the output pin. The simulation above is slowed down so you can see the output does toggle when the correct edge is detected. In a typical NOT gate, the propagation delay is ~ 10 nSec per gate.
Circuit #6 - D Flip Flop (Rising edge Trigger)
Since flip flops contain multiple gates and they get tedious to draw, the above is a standard way of drawing a d-flip flop. Note the triangle on the clock input. This symbol represents a "EDGE TRIGGER". If a circle was on the line coming into this, then it would be a "FALLING EDGE TRIGGER" but since no circle is present, it is a "RISING EDGE TRIGGER".