Flip Flops and Latches


Circuit #1 - SR Flip-Flop (NOR)

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SR - Flip Flop (NOR) Truth Table

SetResetQNot Q
00QlastNot Qlast
0101
1010
11Illegal



Circuit #2 - Gated SR Flip-Flop (NOR)

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Gated SR - Flip Flop (NOR) Truth Table

SetResetGATEQNot Q
XX0QlastNot Qlast
001QlastNot Qlast
10110
01101
111Illegal

X - Don't Care


Circuit #3 - SR Flip-Flop (NAND)

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SR - Flip Flop (NAND) Truth Table

NOT SetNOT ResetQNot Q
11QlastNot Qlast
1001
0110
11Illegal

As with the NOR Flip Flop, A gate can be added to the NAND Flip Flop.


Circuit #4 - D Latch

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D Latch
DCQNot Q
X0QlastNot Qlast
1110
0101



Circuit #5 - Edge Trigger

Rising Edge

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Falling Edge

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These circuits allow the latch to be triggered (clocked) on the rising or falling edge of a pulse instead on just the ON GATE used in the previous examples.

These circuits work due to PROPAGATION DELAY. Propagation delay is the TIME it takes for a change in the input to be seen on the output pin. The simulation above is slowed down so you can see the output does toggle when the correct edge is detected. In a typical NOT gate, the propagation delay is ~ 10 nSec per gate.


Circuit #6 - D Flip Flop (Falling edge Trigger)

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Since flip flops contain multiple gates and they get tedious to draw, the above is a standard way of drawing a d-flip flop. Note the triangle on the clock input. This symbol represents a "EDGE TRIGGER". If a circle was on the line coming into this, then it would be a "FALLING EDGE TRIGGER" but since no circle is present, it is a "RISING EDGE TRIGGER".


Circuit #7 - JK Flip Flop (With Async Preset Clear)

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JK - Flip Flop (with Async Preset and Clr) Truth Table

JKClock/Pre/ClrQ/Q
XX0,1,↓11QlastNot Qlast
0011QlastNot Qlast
101110
011101
1111Not Qlast Qlast
xxx0101
xxx1010

X - Don't Care