TECH 3232
TECH 3232
Digital Technology
Fall 2020

Instructor Info

Daniel Kohn
Office ET218
Phone: 678-4515
Office Hours

Course Info

Course Policies
Formal Report Guide
GradeWatch Access
Submit Assignments
Assignment Feedback


No textbook is required for this class. Materials used in the class are taken from Floyd, Digital Fundamentals (any edition). Other online references are listed below:
All About Circuits Volume IV - Digital
Digital Logic Design

Parts Kit

Since we will be starting the class in a Virtual mode, the instructor has made parts kits for the semester. You are required to pick up the parts kit the first week of the semester by Signing Up for an Appointment and then coming to ET227 during that time to pick up the kit and sign a Equipment Signout Form. Please note that failure to return the lab kit by the end of the semester will result in an "F" for the course, so make sure you return it.

Any broken components can be replaced by the department, but that will mean coming to campus to replace the component, so be extreamly careful with your parts and wait for instructions before attempting to remove parts from the protoboard).


SimcirJS (set and get)


EasyEDA Online Schematic Cad. Video for using instructor's parts library is HERE
Eagle Cad

Online Class

Because of the Covid-19 Virus, TECH3232 will start via Zoom web based video conferencing at the normal class time by clicking on icon (below).

I will also be available during our lab time to assist via Zoom as well.

Classes will be recorded for future reference.

If you have never used ZOOM before, you might want to check out this Video Tutorial and the log in instructions. It is best if you have a mic. A Camera is not required, but I do like seeing who I am talking to. If you do not have a mic, you can ask questions via the Chat function as well. If using a mic, make sure you know how to mute/unmute (to ask questions) and ensure you know how to share your screen so I can see the issues you are having when asking a question on assignments.

Passcode 400677

Video of Lectures

I will be posting the lectures to OneDrive (CLICK HERE) for you to veiw anytime.

Course Outline

Aug 17Welcome
Course Policies
Intro to Digital
 Chp 1 PPT 
Aug 19
Number Systems
Number Systems (Bin, Hex, Oct)Chp 2 PPT (w/worked problems)Assignment #1 - Number Conversions (due Aug 24 by start of class. Submit via same link for instant feedback AND submit hand written work HERE as a pdf of photographed hand written work for full credit!
Aug 24Basic GatesChp 3Chp 3 PPT
Lab #1 - Basic Logic Gates. Type URL to your Youtube Video for "Demonstrate the circuit to the instructor". Video MUST show all possible inputs (run the full truth table). Due start of next weeks lab via file submission on class website.
Aug 26Basic Gates (Cont)

Logic Circuits
Combining Gates
Deriving Truth Table
Deriving Boolean Equation
 Whiteboard Notes
Typed notes (Previous semester)

HW #2 - Due next class (Aug 31) at start of class (via file submission as .docx file with typed answers).
Aug 31Boolean Whiteboard
Notes (Prev Year)
Lab #2 - filled in DOCX file and simulation due start of next week's lab.
Sep 2Boolean (Cont) WhiteboardHW #3 Due start of class Sep 9. Can be submitted as PDF or DOCX
Sep 7No Class (Labor Day)   
Open Sep 7
Due Sep 9
all material covered up to the start of boolean algebra, Lab #1 and Lab #2 (exclude question on boolean)
  Test #1 - follow instructions on test. Due start of class on 9/9 via class website online submission.
Sep 9Boolean (Cont)
Intro SOP and Demorgan
Demorgan's Simulations
SOP/POS Handout
SOP/POS Simulation
Lab #3 - Due in one week.

HW #4 - Due Start of next class.
Sep 14Go over HW #4

Universal Gates

 Universal GatesHW #5 - Due start of next class via online submission.
Sep 16Go Over HW #5

Test Review
  Lab #4 - Due in one week. Schematics will be drawn using EasyEDA.
Sep 21TEST #2
Boolean, Universal Gates.

There will also be questions starting from SOP/POS equations derived from T.T. and equations derived from circuits
  Test #2 - To access the test, click on link and use your last name (first letter of your last name will be caps) and that last 4 digits of your U number.

Once you log in you will have 2 hours to submit the test via the submission system (as a docx or pdf file).

We will NOT have class, but I will be available during that time if you have questions about the test (so you might want to wait until an hour before class time to start the test).

The test will be available by Sat Sep 19 by 10am Sun Sep 20 at 3:15pm and will taken down at the end of the class period, Monday Sep 21 Tues Sep 22 @3:15pm.

Lab is NOT CANCLED, we will have our normal lab!
Sep 23Go over Test #2

K-Maps No Lab Tonight
(Lab #4 still due at start of lab time)

HW #6 - Due Sep 30 at start of class.
Sep 28K-Maps (cont)

Practical Example (with Don't Cares)
  Lab #5 - Formal Lab Report due at start of your lab in 2 weeks via electronic submission.

As promissed, there is now a EasyEDA parts library for the Kit of Parts you recieved at the start of the semester. See THIS VIDEO on how to gain access and use the library.
Sep 30Go Over HW #6

Binary Addition / Subtraction

2's Complement

 Lecture Notes

+/- Simulation
HW #7 - due start of next class.
Oct 5Complex TTL Devices Lecture NotesLab #6 - Due in one week. Here is the Full Sized Schematic for the 4 bit adder and a 7-Seg LED Datasheet.
Oct 7TEST #3
  Test #3 - follow instructions on website to access test.
Oct 12Go Over Test #3

Go Over 2s Comp HW and review

  HW #7b - due start of next class.

Lab #7 - Due by end of lab. Follow instructions in link.
Oct 14Intro to Latches and Flip Flops Lecture Notes
Oct 19   Lab 8
Simulation can be found Here.

HW #8 - Go the the link, log in with the digit 0 after your name and using the last 4 digits of your U number and select the Flip Flop assignment. Fill in the correct answers for each timing diagram (using underscore and minus for Low and High respectively). When submitted review your mistakes. If you missed more than one, repeat (incrementing the digit after your name and your U number (last 4 digits) by one each time until you get at least 7 out of 8).

Dues: Start of next class.

Grading: 5 points off for each addititional attempt.
Oct 21TEST #4
Complex TTL including:
•Half Adders
•Full Adders
Binary addition (with 2's Comp)

Anything after K-maps to the start of FF/Latches
  Test #4 - To access the test, click on link and use your last name (first letter of your last name will be caps) and that last 4 digits of your U number.

When completed, submit the test via the class file submission system (as a .pdf or .docx file).

We will NOT have class, but I will be available during that time if you have questions about the test.

The test is due at the END of class time.

Lab is NOT CANCLED, we will have our normal lab!

Reference Links

Common IC's
Boolean Algebra Rules
Universal Gates
TTL Data Book (ON-Semi 2.5 MB)
TTL Pocket Databook (TI 4.9 MB)