TECH 3232
TECH 3232
Digital Technology
Fall 2018

Instructor Info

Daniel Kohn
Office ET218
Phone: 678-4515
Office Hours

Course Info

Course Policies
Formal Report Guide
GradeWatch Access
Submit Assignments


All About Circuits Volume IV - Digital
Digital Logic Design



Course Outline

Aug 27Welcome
Course Policies
Intro to Digital
 Chp 1 PPT 
Aug 29
Number Systems
Number Systems(Bin, Hex, Oct)Chp 2 PPT (instructors)Assignment #1 - Number Conversions (due in one week). Submit via on-line submission (for instant feedback)AND submit hand written work for full credit! Due Sep 5 at start of class.
Sep 3Labor Day (No Class)   
Sep 5Basic GatesChp 3Chp 3 PPT

note: on the PPT quiz, #5 answer is incorrect, it should be a XNOR gate
Sep 10Logic Circuits
Combining Gates
Deriving Truth Table
Deriving Boolean Equation
 Notes (Example #1)

HW #2 - Due in one week (Sep 17) at start of class.
Sep 12Lab #1 Discussion
Meet in Lab at 5:30pm
  Lab #1 - Basic Logic Gates. Due at end of lab (paper copy).
Sep 17Boolean Notes 
Sep 19Boolean (Cont) NotesLab #2 - due end of lab

HW #3 Due start of class Sep 24.
Sep 24No Class - Instructor Ill   
Sep 26TEST #1
all material covered before Sep 17 and Lab #1
  Lab #3 - Due at end of lab (paper copy + Simulation).
Oct 1Discuss Test #1

 Lecture Notes
HW #4 Due start of class Oct 3.
Oct 3Universal Gates Lecture Notes (Universal Gate Conversion Charts)HW #5 - Due Friday by 3pm

Lab #4 - due end of lab.

Logic Probe Reading
Oct 8Review for Test   
Oct 10TEST #2
Boolean, Universal Gates
Oct 15Fall Break (No Class)   
Oct 17K-MapsRules HW #6 - Due Oct 22 at start of class.
Oct 22K-Maps (cont)   
Oct 24Eagle Cad

K-Map Minimizer
  Lab #5 - Formal Lab Report due Nov 7 at start of lab (electronically and printout).
Oct 29Binary Addition / Subtraction

2's Complement

2's CompLecture NotesHW #7 - due start of next class.
Oct 31Complex TTL Devices Lecture NotesLab #6 - Due end of lab.
Nov 5TEST #3
Nov 7ALU
Intro to Flip Flops and Latches
555 Timer Notes

555 Notebook
Lecture Notes
HW #8 - Due by start of class monday. Follow instructions in link.

Lab #9 - due at start of next week's lab.

Note: it is suggested that the circuit be built on the student's own protoboard and that you leave the circuit (with values from the 1st circuit) on your protoboard so you can use it as your function generator for the final design project.
Nov 12Latches and Flip Flops (cont) Timing Diagram Practice (select Flip Flop from assignment list) 
Nov 14Latches and Flip Flops (cont)

Class and lab cancled due to university closing (inclement weather)
  Lab 8
Arduino Code
Digital Analyzer File

Due Start of next week's lab via online submission. Every student will submit their own (using the group's Digital Analyzer captures). Make sure the answer questions.
Nov 19Lab 8 Demo (in class)

Counter Project Discussion
  Complete Lab #8 given the captures from class.

Figure 1
Figure 2
Figure 3

Due Nov 26 at start of class.

Final Lab Project - Due on or before Dec 12, 2018 by 3pm. Please submit paper and schematic via online submission. You are required to demonstrate your circuit before it is dismantled.

You can use the 555 timer from Lab #9 as the clock for the circuit or a Function Generator (Setup Instructions).

Digital Analyzer Setup File (download file and put on a recently virus scanned thumbdrive).

The name and password for the Digital Analyzers are:


Nov 21Thanksgiving (no class or lab)    
Nov 26More discussion on Counter Project   
Nov 28Test Review   
Dec 3TEST #4
Binary Math (2s Comp), Adder's, Complex Devices, ALU, Flip Flops and Latches (S-R, D, J-K Pre/Clr) including Timing Diagrams
Dec 5Hand back Test #4

Review for Exam
Dec 12Comprehensive Exam   

Reference Links

Common IC's
Boolean Algebra Rules
TTL Data Book (ON-Semi 2.5 MB)
TTL Pocket Databook (TI 4.9 MB)

Requested Links

K-Map Software (click on the (zip icon) for free version)