Email: dekohn@memphis.edu

Office ET218

Phone: 678-4515

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Digital Logic Design

Date | Topic | Reading | Handouts | Assignments |
---|---|---|---|---|

Aug 27 | Welcome Course Policies Intro to Digital | Chp 1 PPT | ||

Aug 29 | Number Systems | Number Systems(Bin, Hex, Oct) | Chp 2 PPT (instructors) | Assignment #1 - Number Conversions (due in one week). Submit via on-line submission (for instant feedback) submit hand written work for full credit! Due Sep 5 at start of class.AND |

Sep 3 | Labor Day (No Class) | |||

Sep 5 | Basic Gates | Chp 3 | Chp 3 PPT Simulations note: on the PPT quiz, #5 answer is incorrect, it should be a XNOR gate | |

Sep 10 | Logic Circuits Combining Gates Deriving Truth Table Deriving Boolean Equation | Notes (Example #1) Simulations | HW #2 - Due in one week (Sep 17) at start of class. | |

Sep 12 | Lab #1 Discussion Meet in Lab at 5:30pm | Lab #1 - Basic Logic Gates. Due at end of lab (paper copy). | ||

Sep 17 | Boolean | Notes | ||

Sep 19 | Boolean (Cont) | Notes | Lab #2 - due end of lab HW #3 Due start of class Sep 24. | |

Sep 24 | No Class - Instructor Ill | |||

Sep 26 | TEST #1all material covered before Sep 17 and Lab #1 | Lab #3 - Due at end of lab (paper copy + Simulation). | ||

Oct 1 | Discuss Test #1 Demorgan SOP vs POS | Lecture Notes Simulations | HW #4 Due start of class Oct 3. | |

Oct 3 | Universal Gates | Lecture Notes (Universal Gate Conversion Charts) | HW #5 - Due Friday by 3pm Lab #4 - due end of lab. Logic Probe Reading | |

Oct 8 | Review for Test | |||

Oct 10 | TEST #2Boolean, Universal Gates | |||

Oct 15 | Fall Break (No Class) | |||

Oct 17 | K-Maps | Rules | HW #6 - Due Oct 22 at start of class. | |

Oct 22 | K-Maps (cont) | |||

Oct 24 | Eagle Cad K-Map Minimizer | Lab #5 - Formal Lab Report due Nov 7 at start of lab (electronically and printout). | ||

Oct 29 | Binary Addition / Subtraction 2's Complement Adders | 2's Comp | Lecture Notes | HW #7 - due start of next class. |

Oct 31 | Complex TTL Devices | Lecture Notes | Lab #6 - Due end of lab. | |

Nov 5 | TEST #3K-Maps | |||

Nov 7 | ALU 555 Intro to Flip Flops and Latches | 555 Timer Notes 555 Notebook | Lecture Notes Simulations | HW #8 - Due by start of class monday. Follow instructions in link. Lab #9 - due at start of next week's lab. Note: it is suggested that the circuit be built on the student's own protoboard and that you leave the circuit (with values from the 1st circuit) on your protoboard so you can use it as your function generator for the final design project. |

Boolean Algebra Rules

TTL Data Book (ON-Semi 2.5 MB)

TTL Pocket Databook (TI 4.9 MB)