TECH 3232
TECH 3232
Digital Technology
Fall 2017

Instructor Info

Daniel Kohn
Office ET218
Phone: 678-4515
Office Hours

Course Info

Course Policies
Formal Report Guide
GradeWatch Access
Submit Assignments


All About Circuits Volume IV - Digital
Digital Logic Design
Introduction to Digital Logic



Course Outline

Aug 29Welcome
Course Policies
Aug 31Intro to Digital
Number Systems
Number Systems(Bin, Hex, Oct)Chp 1 PPT
Chp 2 PPT (instructors)
Assignment #1 - Number Conversions (due in one week). Submit via on-line submission (for instant feedback)AND submit hand written work for full credit! Due Sep 7 at start of class.
Sep 5Basic GatesChp 3Chp 3 PPT
Sep 7Logic Circuits
Combining Gates
Deriving Truth Table
Deriving Boolean Equation
Drawing Circuit Diagrams
 Notes (Example #1)

HW #2 - Due in one week (Sep 14) at start of class.
Sep 12Boolean Algebra

Lab #1 Discussion
 Class NotesLab #1 - Basic Logic Gates. Due at end of lab (paper copy).
Sep 14Boolean (Cont) Notes (note these are the problems worked in class, but reworked after the fact, so the steps might be slightly different)HW #3 Due start of next class (Sep 19)
Sep 19Boolean (Cont)  Lab #2 - due end of lab

HW #4 Due start of class Sep 26.
Sep 21TEST #1
all material covered before Sep 12 and Lab #1
Sep 26Discuss Test #1
 Lecture Notes
Lab #3 - due end of lab

HW #5 Due start of class Sep 28.
Sep 28Universal Gates Lecture Notes (Universal Gate Conversion Charts) 
Oct 3Test Review  Lab #4 - due end of lab.

Logic Probe Reading
Oct 5TEST #2
Boolean, Universal Gates
Oct 10Go over Test #2

Intro to K-Maps
Rules Lab #5 - Formal Lab Report due Oc 24 at start of lab (electronically and printout).

Rough Draft (not required, but strongly encouraged) will be accepted on or before Sun Oct 15 (one submission per student) and will be returned on Oct 19 at start of class.
Oct 12K-Maps (Cont)

Eagle Cad

K-Map Minimizer
Understanding K-Maps (Video)
Understanding Dont Care's (video)
Oct 17Fall Break (No Class)   
Oct 19K-Maps (cont)

  HW #6 - Due Oct 24 at start of class.
Oct 24Complex TTL Devices  Lab #6 - Due end of lab.
Oct 26Review for Test

More Complex Devices
Oct 31TEST #3

Reference Links

Boolean Algebra Rules
Boolean Algebra Checker
TTL Data Book (ON-Semi 2.5 MB)
TTL Pocket Databook (TI 4.9 MB)
Common IC's

Requested Links

All Electronics / Breadboards
K-Map Software
Eagle Cad (Demo Version)
Eagle Cad (older 32bit version)