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Digital Logic Design

Introduction to Digital Logic

Date | Topic | Reading | Handouts | Assignments |
---|---|---|---|---|

Aug 29 | Welcome Course Policies | |||

Aug 31 | Intro to Digital Number Systems | Number Systems(Bin, Hex, Oct) | Chp 1 PPT Chp 2 PPT (instructors) | Assignment #1 - Number Conversions (due in one week). Submit via on-line submission (for instant feedback) submit hand written work for full credit! Due Sep 7 at start of class.AND |

Sep 5 | Basic Gates | Chp 3 | Chp 3 PPT Simulations | |

Sep 7 | Logic Circuits Combining Gates Deriving Truth Table Deriving Boolean Equation Drawing Circuit Diagrams | Notes (Example #1) Simulations | HW #2 - Due in one week (Sep 14) at start of class. | |

Sep 12 | Boolean Algebra Lab #1 Discussion | Class Notes | Lab #1 - Basic Logic Gates. Due at end of lab (paper copy). | |

Sep 14 | Boolean (Cont) | Notes (note these are the problems worked in class, but reworked after the fact, so the steps might be slightly different) | HW #3 Due start of next class (Sep 19) | |

Sep 19 | Boolean (Cont) | Lab #2 - due end of lab HW #4 Due start of class Sep 26. | ||

Sep 21 | TEST #1all material covered before Sep 12 and Lab #1 | |||

Sep 26 | Discuss Test #1 SOP vs POS | Lecture Notes Simulations | Lab #3 - due end of lab HW #5 Due start of class Sep 28. | |

Sep 28 | Universal Gates | Lecture Notes (Universal Gate Conversion Charts) | ||

Oct 3 | Test Review | Lab #4 - due end of lab. Logic Probe Reading | ||

Oct 5 | TEST #2Boolean, Universal Gates | |||

Oct 10 | Go over Test #2 Intro to K-Maps | Rules | Lab #5 - Formal Lab Report due Oc 24 at start of lab (electronically and printout). Rough Draft (not required, but strongly encouraged) will be accepted on or before Sun Oct 15 (one submission per student) and will be returned on Oct 19 at start of class. | |

Oct 12 | K-Maps (Cont) Eagle Cad K-Map Minimizer | Understanding K-Maps (Video) Understanding Dont Care's (video) | ||

Oct 17 | Fall Break (No Class) | |||

Oct 19 | K-Maps (cont) Adders | HW #6 - Due Oct 24 at start of class. | ||

Oct 24 | Complex TTL Devices | Lab #6 - Due end of lab. | ||

Oct 26 | Review for Test More Complex Devices | |||

Oct 31 | TEST #3K-Maps |

Boolean Algebra Checker

TTL Data Book (ON-Semi 2.5 MB)

TTL Pocket Databook (TI 4.9 MB)

Common IC's

K-Map Software

Eagle Cad (Demo Version)

Eagle Cad (older 32bit version)