|Aug 31||Intro to Digital|
|Number Systems(Bin, Hex, Oct)||Chp 1 PPT|
Chp 2 PPT (instructors)
|Assignment #1 - Number Conversions (due in one week). Submit via on-line submission (for instant feedback)AND submit hand written work for full credit! Due Sep 7 at start of class.|
|Sep 5||Basic Gates||Chp 3||Chp 3 PPT|
|Sep 7||Logic Circuits|
Deriving Truth Table
Deriving Boolean Equation
Drawing Circuit Diagrams
|Notes (Example #1)|
|HW #2 - Due in one week (Sep 14) at start of class.|
|Sep 12||Boolean Algebra|
Lab #1 Discussion
|Class Notes||Lab #1 - Basic Logic Gates. Due at end of lab (paper copy).|
|Sep 14||Boolean (Cont)||Notes (note these are the problems worked in class, but reworked after the fact, so the steps might be slightly different)||HW #3 Due start of next class (Sep 19)|
|Sep 19||Boolean (Cont)||Lab #2 - due end of lab|
HW #4 Due start of class Sep 26.
|Sep 21||TEST #1|
all material covered before Sep 12 and Lab #1
|Sep 26||Discuss Test #1|
SOP vs POS
|Lab #3 - due end of lab|
HW #5 Due start of class Sep 28.
|Sep 28||Universal Gates||Lecture Notes (Universal Gate Conversion Charts)|
|Oct 3||Test Review||Lab #4 - due end of lab.|
Logic Probe Reading
|Oct 5||TEST #2|
Boolean, Universal Gates
|Oct 10||Go over Test #2|
Intro to K-Maps
|Rules||Lab #5 - Formal Lab Report due Oc 24 at start of lab (electronically and printout).|
Rough Draft (not required, but strongly encouraged) will be accepted on or before Sun Oct 15 (one submission per student) and will be returned on Oct 19 at start of class.
|Oct 12||K-Maps (Cont)|
|Understanding K-Maps (Video)|
Understanding Dont Care's (video)
|Oct 17||Fall Break (No Class)|
|Oct 19||K-Maps (cont)|
Binary Addition / Subtraction
|2's Comp||Lecture Notes||HW #6 - Due Oct 24 at start of class.|
|Oct 24||Complex TTL Devices||Lab #6 - Due end of lab.|
|Oct 26||Review for Test|
More Complex Devices
|Oct 31||TEST #3|
|Lab #7 - Due by end of lab. Follow instructions in link.|
|Nov 2||Latches and Flip Flops|
up to J-K
|Nov 7||Latches and Flip Flops (cont)||Lab 8|
Full Sized Schematic
Digital Analyzer File
Due Start of next week's lab via online submission. Every student will submit their own (using the group's Digital Analyzer captures). Make sure the answer questions.
|Nov 9||Latches and Flip Flops (cont)||Lecture PPT||HW #7 - see email sent Nov 9.|
|Nov 14||555 Timer||555 Timer Notes|
|Lab #9 - due at start of next week's lab.|
Note: it is suggested that the circuit be built on the student's own protoboard and that you leave the circuit (with values from the 1st circuit) on your protoboard so you can use it as your function generator for the final design project.
|Nov 16||Design Project||Final Lab Project - Due on or before Dec 12, 2017 by 3pm. Please submit paper and simulation file(s) via online submission. You are required to demonstrate your circuit before it is dismantled.|
You can use the 555 timer from Lab #9 as the clock for the circuit or a Function Generator (Setup Instructions).
Digital Analyzer Setup File (download file and put on a recently virus scanned thumbdrive).
The name and password for the Digital Analyzers are:
To edit a simulation you can use THIS LINK.
|Nov 21||TEST #4|
Binary Math (2s Comp), Adder's, Complex Devices, Flip Flops and Latches (S-R, D, J-K Pre/Clr) including Timing Diagrams
|Nov 23||Thanksgiving Break|
|Nov 28||Hand Back Test 4|
|Nov 30||Review for Exam|
(Class / Lab Time)
Comprehensive exam (but special emphasis on Counters)